1. Field of Use
This invention relates generally to data processing systems and more particularly to error correction apparatus included within the memory of a data processing system.
2. Prior Art
As discussed in greater detail in the referenced related patent application, in order to increase memory reliability notwithstanding attendant increases in error detection and correction circuits, at least one system utilizes codes which improve upon the modified Hamming SEC/DED codes and simplify the memory circuit implementation as well as provide faster and better error detection capability. This arrangement is described in a paper "A Class of Optimal Minimum Odd-Weight-Column SEC/DED Codes" by M. Y. Hsiao which appears in the publication "IBM Journal of Research and Development", July, 1970.
The paper describes the construction of such codes in terms of a parity check matrix H. The selection of the columns of the H matrix for a given (n, k) code is based upon the following constraints:
1. Every column should have an odd number of one's;
2. The total number of one's in the H matrix should be a minimum; and,
3. The number of one's in each row of the H matrix should be made equal or as close as possible to the average number.
Errors are indicated by analyzing the syndromes formed from the data and check code bits. An odd number of syndrome bits indicates a single error while an even number of syndrome bits indicates a double or uncorrectable error.
In the above mentioned arrangement as well as other prior art systems, while reducing the amount of circuits by observing the constraints mentioned above, such systems still require large numbers of multi-input AND error locator circuits as well as circuits for generating parity bit signals for the data read out of memory. Thus, the disadvantages of such arrangements are their higher cost, complexity in implementation and lower reliability. That is, if the implementation requires fewer circuits and connections, its chance of failure is decreased. Also, such systems may require construction of special circuits which would also result in higher cost.
Accordingly, it is a primary object of the present invention to provide apparatus for locating errors which has a high reliability and employs standard circuits.
It is another object of the present invention to provide apparatus for locating errors and for concurrently providing correct parity for the data when read out.
It is a more specific object of the present invention to provide apparatus which both locates errors and provides correct parity for the read out data in a manner which requires a minimum of additional circuits.